About the Role
You lead Verilog RTL for FPGA and ASIC. You run reviews. You mentor two juniors.
Responsibilities
- Design and implement high-performance digital circuits in Verilog/SystemVerilog
- Lead architectural discussions and code reviews
- Collaborate with verification and physical design teams
- Optimize designs for performance, power, and area
- Mentor junior engineers and establish best practices
Requirements
- 5+ years of professional Verilog/SystemVerilog experience
- Strong understanding of digital design principles
- Experience with FPGA tools (Xilinx/Vivado or Altera/Quartus)
- Knowledge of design patterns and best practices
- Excellent communication skills
Nice to Have
- ASIC design experience
- Formal verification knowledge
- Python or scripting experience
- Knowledge of system-level design tools
Benefits
- Competitive salary and equity
- Health insurance (medical, dental, vision)
- Provident Fund (PF) and gratuity
- Flexible work schedule
- Professional development budget
- Home office setup stipend